1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device in which charging damage of a gate oxide film is reduced.
2. Description of the Related Art
There are known many processes using plasma in a semiconductor manufacturing process. There are problems in the plasma using processes. For instance, a damage to a gate oxide film of a metal oxide semiconductor (MOS) transistor is brought about, or the yield of large-scale integrated circuits (LSI) is reduced. As a device size becomes smaller and the gate oxide film becomes thinner, the degradation becomes worse, and the reliability is further reduced. The mechanism by which the gate oxide film is damaged will be described below with reference to the attached drawings.
FIGS. 1A and 1B are drawings showing a semiconductor device according to a first conventional example. FIG. 1A is a plan view of the semiconductor device, and FIG. 1B is a cross-sectional view of the semiconductor device. A diffusion layer 30 is formed in a region surrounded by a field oxide film 20 for isolating an element, on a surface of a semiconductor substrate 10. A gate electrode 50 is disposed on a gate oxide film 40 on the semiconductor substrate 10. A first insulating film 60 is disposed on the whole portion including the gate electrode 50 and the field oxide film 20. The gate electrode 50 is connected to a contact 70 disposed to pass through the first insulating film 60, and the contact 70 is connected to a first wiring 80 disposed on the first insulating film 60.
The processes using plasma are typically adopted in a process for forming the first wiring 80 and the post-process thereof, among the processes for manufacturing the semiconductor device shown in FIGS. 1A and 1B. For example, this may include a plasma etching method for forming a wiring, a plasma ashing method for removing resist, a plasma chemical vapor deposition (CVD) method for forming an interlayer insulating film, and a plasma etching method for forming a via-hole passing through an interlayer insulating film.
There exist ionized ions and electrons in the plasma. When the semiconductor substrate having the elements as shown in FIGS. 1A and 1B is exposed to plasma in which a balance between positive and negative charges is broken down, the charges enter from a surface of a conductor exposed in the plasma, e.g., the first wiring 80 in a case of FIGS. 1A and 1B, and flow through the gate electrode 50 and the gate oxide film 40 into the semiconductor substrate 10. A current due to the electric charges brings about the electric wear out of the gate oxide film 40, resulting in low reliability of the gate oxide film 40 for long term usage. This is an electrical damage because of the plasma. Hereinafter, this is referred to as a plasma damage.
Thus, a conductor directly exposed to the plasma acts as an antenna for collecting electrical charges. Therefore, the larger the antenna is, the severer the plasma damage becomes. An "antenna ratio" is used as an index for quantitatively representing the degree of the plasma damage. The antenna ratio is defined as a ratio of an area of the conductor exposed to the plasma to an area of the gate oxide film. Hence, in order to reduce the plasma damage, it is necessary to reduce the antenna ratio as small as possible. That is, an area or a length of the wiring connected to the gate electrode is required to be small.
Several processes may cause the plasma damage. For example, they are an etching process for etching the wiring, an ashing process for stripping a resist after the wiring etching, a process for forming an interlayer insulating film by means of a plasma CVD method after the wiring formation, and a via-hole etching process for forming an opening to the insulating film. According to an experiment, the plasma damage brought about by the etching process for forming the wiring is the severest. The plasma damages caused in another plasma processes are practically much lower than that of the wiring etching process.
Next, considering the damage in the plasma etching for forming the wiring, an example of reducing the damage will be described below.
FIGS. 2A and 2B are diagrams showing a second conventional example of a semiconductor device designed to reduce the damage. This example is disclosed in Japanese Laid Open Patent Disclosure (JP-A-Heisei 6-204467). FIG. 2A is a plan view of the semiconductor device, and FIG. 2B is a cross-sectional view of the semiconductor device.
The semiconductor device shown in FIGS. 2A and 2B is formed is the same as in the first conventional example shown in FIGS. 1A and 1B, until the contact 70 is formed. However, the first wiring is provided to be composed of a wiring section 81 connected to a gate electrode 50 and a wiring section 82 which is not connected to the gate electrode 50. A second insulating film 90 is disposed on the entire surface including the first wiring and a first insulating film 60. First via-holes 101 and 102 are disposed in the second insulating film 90 to be connected to the first wiring sections 81 and 82, respectively. On the second insulating film 90, a second wiring 110 is disposed to be connected through the first via-holes 101 and 102 to the first wiring sections 81 and 82.
The second conventional example shown in FIGS. 2A and 2B is important in that the first wiring 80 is provided to be composed of the wiring section 81 connected to the gate electrode 50 and the wiring section 82 which is not connected to the gate electrode 50. When etching is performed to form the first wiring, only the wiring section 81 connected to the gate electrode 50 functions as the charging antenna for collecting electrical charges. Therefore, in the second conventional example, the small antenna ratio is accomplished.
For example, if the length of the wiring section 81 is 1/10 times shorter than the length of the wiring section 82, the antenna ratio can be also reduced to 1/10. The electrical connection between the first wiring sections 81 and 82 is accomplished by the second wiring 110 above the first wiring. Moreover, an area of the second wiring 110 can be formed sufficiently small. Thus, the plasma damage because of the second wiring 110 can be reduced small. As a result, the plasma damage of the gate oxide film 40 brought about by the etching process can be reduced sufficiently small.
The second conventional example shown in FIGS. 2A and 2B can protect the gate oxide film from the plasma damage in the etching process and the ashing process for the first wiring, and the forming process for the second insulating film 90.
A method for reducing a damage in forming a pad having a large area for connecting a probe or bonding wire is disclosed in JP-A-Heisei 7-235541 and U.S. Pat. No. 5,393,701. As an example, Japanese Laid Open Patent Disclosure (JP-A-Heisei 7-235541) will be described below.
FIGS. 3A and 3B are drawings showing a semiconductor device disclosed in the Japanese Laid Open Patent Disclosure (JP-A-Heisei 7-235541). FIG. 3A is a plan view of the semiconductor device, and FIG. 3B is a cross-sectional view of the semiconductor device.
A semiconductor device shown in FIGS. 3A and 3B is explained as follows. A first wiring is disposed on a first insulating film 60, which is disposed on a semiconductor substrate 10. The first wiring is provided to be composed of a wiring section 82 having a large area a part of which is used as a pad electrode 200, and a wiring section 81 having a small area which is not connected with the wiring section 82. A second insulating film 90 is disposed to have two openings reaching the first wiring. One of the two openings is a pad opening 190 having the same size as that of the pad electrode 200. The other opening is a via-hole 100 which extends to a part of the wiring section 81 and a part of the wiring section 82 through the second insulating film 90. Then, a second wiring 110 is disposed at two openings. A second wiring section 111 of the second wiring 110 is disposed in the via-hole 100 to connect the wiring section 81 and the wiring section 82. A second wiring section 112 of the second wiring 110 is disposed on the pad opening 190 to cover the exposed part of the wiring section 82.
In a third conventional example shown in FIGS. 3A and 3B, a gate electrode (not shown) is connected to the wiring section 81 having the small area. In this case, since the antenna ratio can be made small, the damage when etching is performed to form the first wiring 80 can be reduced, as in the second conventional example described with reference to FIGS. 2A and 2B. Moreover, the plasma damage can be reduced when the pad opening 190 is formed on the first wiring 80.
The conventional examples shown in FIGS. 2A, 2B and FIGS. 3A, 3B are effective for reducing the plasma damages brought about in the plasma etching processes to form the first wiring 80, to ash resist, to form the second insulating film 90 and to form the first via-hole 100. However, they can not protect the semiconductor device from the damage brought about in the plasma etching process to form the second wiring 110. Especially, as shown in FIGS. 3A and 3B, when the second wiring 110 is formed to be the pad electrode for connecting a probe or a bonding wire, the pad electrode typically have a large area such as about 100.times.100 square microns, and the antenna ratio of the pad electrode is also high. As a result, the forming process of the second wiring 110 causes a severe damage to the gate oxide film.